The present invention relates generally to a current source circuit, more specifically to a current source circuit whose output current can be adjusted from zero linearly and precisely and provide an electronic load receiving the output current with an improved power voltage usage efficiency.
A variable or constant current source circuit is used in many kinds of electronic circuits, such as an offset circuit, a ramp waveform generator and the like. When a current source circuit is used in an offset circuit to offset an output signal from a signal generator, the current from the current source circuit and the output signal from the signal generator are mixed and flow through a termination resistor or a resistor of a load. The offset voltage for the output signal is determined by the voltage across the resistor based on the current from the current source.
A conventional current source is shown in FIG. 1. The emitter of a bipolar NPN transistor 10 receives a supply voltage, such as -15 V, through a resistor 12 and is coupled to the inverting input terminal of an operational amplifier 14 serving as a differential amplifier. The base of the transistor 10 is coupled to the output terminal of the operational amplifier 14 and the collector thereof is connected to a properly biased electronic load circuit and produces a sink output current Iout. A control voltage source 16 providing a voltage Vcnt1 is connected between the non-inverting input terminal of the operational amplifier 14 and the -15 V supply voltage line. Power supply (driving) voltages for the operational amplifier 14 are -15 V and ground voltage. It should be noted that the -15 V power supply voltage is common to the transistor 10 via resistor 12 and the operational amplifier 14.
In the current source circuit shown in FIG. 1, the operational amplifier 14 controls the base of the transistor 10 in order to produce an emitter current equal to Vcnt1/R12, where R12 is the resistance of resistor 12, so that the voltage across resistor 12 will be the same as the voltage of the control voltage source 16 (Vcnt1); the voltage at the inverting input terminal of the amplifier 14 will be equivalent to the voltage present at its non-inverting input terminal. Ignoring the transistor base current, this emitter current is the same as the transistor collector current, Iout. Thus, the output current is variable and will change according to changes in Vcnt1.
Most operational amplifiers require that the output voltage remain between the operational amplifier's supply voltages with about a 2 V margin. In the case of FIG. 1, since the power supply voltages are -15 V and 0 V, the output voltage should be in the range between -13 V and -2 V. With this output voltage range, the control voltage magnitude must stay between +1.3 V and +12.3 V (operational amplifier's output voltage, minus a transistor base emitter voltage drop, minus the negative supply) in order for the operational amplifier to operate properly. This implies that the minimum voltage across resistor 12 is 1.3 V, so that the minimum current Iout is +1.3/R12. Therefore, the output current Iout remains greater than zero and the current source circuit cannot be used to produce small and variable offset currents close to zero or to generate a low speed ramp waveform.
This disadvantage can be overcome by another conventional current source circuit shown in FIG. 2. The difference between the circuits of FIGS. 1 and 2 is that the operational amplifier 14 receives its power supply voltages from a second voltage source. In other words, the lower end of the resistor 12 and the cathode of the voltage source 16 are connected to a power supply voltage of -12.5 V and the operational amplifier 14 receives a power supply voltage of -15 V. The voltage difference between these power supply voltages is 2.5 V because an extra 0.5 V margin is added to 2 V. Since the input voltage range of the operational amplifier 14 is between -13.7 V and -2.7 V (output range minus a base emitter voltage drop), the voltage across the resistor 12 can be set arbitrarily close to OV by adjusting the control voltage source 16. Thus, the minimum output current Iout can be set to zero.
FIG. 3 shows characteristic lines of the emitter voltage VE and the maximum output voltage (collector voltage) Vout of the transistor 10 wherein the control voltage Vcnt1 of the control voltage source 16 is variable in the range between 0 V and 2 V. In FIG. 3, the left vertical axis represents voltage, the right vertical axis represents the control voltage Vcnt1 for setting the output current Iout, and the horizontal axis represents the output current Iout as a percentage of the output current provided when the control voltage Vcnt1 is 2 V. The saturation voltage between the collector and emitter of the transistor 10 is assumed to be 0.5 V.
As will be understood from FIG. 3, a control voltage Vcnt1 equal to 0 V would produce an emitter voltage VE of -12.5 V. The output current Iout increases proportionally to the control voltage Vcnt1. The transistor 10 can operate properly in circumstances where the collector voltage exceeds the emitter voltage VE by the collector-emitter saturation voltage (0.5 V).
When the emitter resistor 12 of FIG. 2 is zero, the maximum output power Pmax delivered to the load is EQU Pmax=(1/RL)[Vcesat+V-s].sup.2.
RL corresponds to the load resistance receiving Iout, Vcesat represents the transistor collector to emitter saturation voltage, and V-s is the negative supply voltage (-12.5 V in the case of FIG. 2). The load takes full advantage of the available collector voltage swing.
When the emitter resistor 12 is non-zero, it reduces the power available to the load resistor. It may be shown that EQU Ioutmax=-(Vcesat+V-s)/RL+R12)
and that the maximum output power delivered to RL is EQU Pmax=RL[(Vsat+V-s)/(RL+R12)].sup.2.
By re-arranging the output power equation, EQU Pmax=(1/RL)[(Vsat+V-s)/(1+R12/RL)].sup.2
the reduced power may be seen as related to a reduction in voltage available at the collector, by a factor of EQU 1/(1+R12/RL).
Accordingly, it may be said that the emitter resistor affects the power voltage usage efficiency of the load receiving the output current.
There are also other considerations with respect to the prior art circuits which employ the bipolar transistor 10. On one hand, it is desirable to use a bipolar transistor having a small stray capacitance between the electrodes thereof in order to prevent high frequency component signals, which may be present in an electronic circuit serving as the load, from penetrating the current source circuit. Moreover, a non-ideal bipolar transistor has limited gain (hfe or .beta.). With limited gain, the transistor flows a base current and the output collector current is less than the emitter current by the amount of this base current. In addition, the transistor gain will vary with temperature as will the base current and therefore the output current Iout will not be stable with temperature.
The error based on the base current can be avoided by exchanging the bipolar transistor 10 in FIG. 1 or 2 with a field effect transistor (FET). In this instance, the gate of the FET is connected to the output terminal of the operational amplifier 14, the source thereof is connected to the inverting input terminal of the operational amplifier 14 and the resistor 12, and the drain thereof acts as the current output terminal. Since no current flows through the gate of the FET, all the source current flows through the drain, thereby obviating the current error problem. However, the FET has a large stray capacitance between the electrodes thereof in comparison with the bipolar transistor, so that the FET will not be able to isolate high frequency signals between the drain and gate as effectively as a bipolar transistor between collector and base.
The current source circuit can be used as an offset circuit for a high frequency signal generator. In this instance, the output currents from both the current source and the signal generator flow through a load or a device under test. The current from the current source circuit generates a voltage across the load which corresponds to the offset voltage of the high frequency signal. When the current source circuit includes a FET in the output stage as discussed hereinbefore, the high frequency signal from the signal generator flows into the current source circuit via electrode stray capacitance of the FET. Thus, it is difficult to accurately apply the high frequency signal to the device under test (DUT) from the signal generator when the offset circuit is attached. The stray capacitance of the FET provides a high frequency by-pass for high frequency signals to follow a path around the DUT.
What is desired is a current source circuit that can change its output current linearly from zero and improves the power voltage usage efficiency of an electronic circuit receiving the output current from the current source circuit. In addition, what is desired is a current source circuit that employs a bipolar transistor having a small stray capacitance between its electrodes and can generate its output current accurately without being affected by the base current.